Currently, there are many known methods used to introduce controllable delays in a circuit path. For example, in an approach, additional delays are added by adding additional logic gates to an input-output path of the circuit. The signal traveling from the input through each logic gate to the output is delayed by the logic gates as each logic gate includes an amount of time delay. Adding logic gates, however, adds complexities and costs to the circuit. In another approach, a transistor coupled to a capacitor serves as a capacitive load to slow down the signal transition or, effectively, delay the signal. This approach requires costly die area to generate the appropriate capacitance value. Different mechanisms to control the delay are needed.
Like reference symbols in the various drawings indicate like elements.